This invention relates to integrated circuit chips; and more particularly, it relates to the testing of clocked logic circuitry on such chips.
By clocked logic circuitry is herein meant any type of logic circuit that receives a clock signal, which is a series of pulses, and which responds to either high-to-low transitions or low-to-high transitions in the pulses. Some examples of clocked logic circuitry are D-type flip-flops, JK-type flip-flops, counters, and shift registers. Hundreds of these kinds of circuits commonly exist in various combinations and interconnections on a single chip.
One characteristic of a clocked logic circuit is that the pulses in the clock signal must have a certain minimum width in order for the clocked logic circuit to operate properly. However, making the width of the clock pulses larger inherently lowers the clock frequency and thus lowers the speed at which the clocked logic circuitry operates. Often, the clocked logic circuitry is performing some function in which the speed of execution is critical and must be minimized. Thus, a need exists for determining just how small the width of the pulses in the clock signal can be made without causing the clocked logic circuitry to operate improperly.
Currently, as well as in the past, various commercially available instruments called "pulse generators" were used to generate narrow width clock pulses as test signals for the clocked logic chips. However, one of the problems with such instruments is that at any one time, they merely generate pulses of a simple width, and manual interaction with the instrument is required to change that pulsewidth. Commercially available pulse generators do not generate variable width pulse sequences in which each successive pulse is automatically increased or decreased, and as is shown later herein, such variable width pulse sequences are very useful in testing clocked logic chips.
Another problem with commercially available pulse generators is that today's clocked logic chips are too fast to be fully tested by the instrument. That is, the clocked logic circuitry on the chip will operate properly even when it is given the narrowest clock pulses which the instrument can deliver. For example, the latest state-of-the-art pulse generator from Hewlett Packard is the HP model 8131A; and the narrowest pulses which it can generate are 500 picoseconds wide. This is documented in the 1989 Hewlett Packard TEST AND MEASUREMENT catalog at page 433. That page also lists the narrowest pulses from earlier pulse generator models at 2 nanoseconds, 4 nanoseconds, and larger. But, by comparison, the MCA3 clocked logic cells from Motorola operate properly with clock pulses that are less than 300 picoseconds wide.
Still another problem with commercially available pulse-generating instruments is that they are very expensive. For example, the above-referred HP 8131A instrument, without any optional features or accessories, costs $14,300. This is documented on page 437 of the above-referenced TEST AND MEASUREMENT catalog.
Accordingly, a primary object of this invention is to overcome both the performance and the expense problems which are pointed out above.